Clock signals are typically used to synchronize data signals in electronic devices. In certain applications, multiple clock signals may be provided in a single device. As these clock signals propagate through the device, they pass through clock signal paths of different lengths and complexity depending on the particular routing of the clock signal paths. As a result, different clock signals may experience different delays caused by these clock signal paths and thus may exhibit clock skew relative to each other.
In order to minimize the effects of such clock skew, additional delays may be introduced into the clock signal paths of individual clock signals to align the clock edges of different clock signals such that the clock edges arrive at a given destination at approximately the same time. For example, in conventional application-specific integrated circuits (ASICs), the routing of clock signals is typically hardwired into the design of integrated circuits. In such applications, clock skew can typically be predicted and corrected to satisfactory accuracy through the introduction of predictable delays into the clock signal paths for hardwired clock signal paths.
However, for programmable logic devices (PLDs) such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), the routing of clock signals is largely dependant on the user-configurable designs implemented in the PLDs. As such, clock signal delays and the resulting clock skew can vary widely depending on the particular configuration of a PLD.
These problems are further complicated in implementations where different portions of a PLD are synchronized by various clock signals corresponding to different clock domains. In this regard, when data signals are passed between different clock domains, data signals synchronized by a first clock signal of a first frequency may be provided to flip flops synchronized by a second clock signal of a second frequency. In this case, it is important that the clock edges of the different clock signals be coordinated in order to meet the hold time and setup time constraints associated with the flip flops.
Nevertheless, conventional techniques used to minimize clock skew fail to satisfy such hold time and setup time constraints and thus may cause clock-to-clock data transfers to fail. Accordingly, there is a need for an improved approach for reducing the effects of clock skew between multiple clocks to permit successful data transfers between different clock domains of a PLD.